This application claims priority to Korean Application Nos. 2000-27504, filed May 22, 2000, and 2000-71031, filed Nov. 27, 2000, the disclosures of which are hereby incorporated herein by reference.
The present invention relates to integrated circuit memory devices and, more particularly, to dynamic random access memory devices and methods of operating same.
Semiconductor memory devices such as dynamic random access memory (DRAM) devices have become highly-integrated and operate at higher speed to improve system performance. A synchronous DRAM that operates in-sync with a system clock has been developed for high-speed operation, and data transmission speed has been dramatically increased by advances in synchronous DRAM technology.
However, since data typically must be inputted and outputted in one cycle of the system clock in the synchronous DRAM, there may be limitations when attempting to increase data bandwidth flowing between the synchronous DRAM and a DRAM controller. To address this limitation, dual data rate (DDR) synchronous DRAMs, which input and output data in synchronization with a rising edge and a falling edge of the clock, have been developed to increase data transmission bandwidth. A data strobe signal is typically used in a DDR synchronous DRAM in order to minimize timing margin losses caused by timing skew when reading and writing operations are being performed on DDR DRAMs in systems containing many modules. Timing margin losses may also be caused by process variations, voltage temperature (PVT) variations and differences in propagation delay from a memory controller to each of a plurality of memory modules or from each of the memory modules to the memory controller.
Referring now to FIG. 1, a block diagram of a system using a conventional DDR synchronous DRAM is illustrated. FIG. 2 is a timing diagram illustrating a method for writing data into the conventional DDR synchronous DRAM, and FIG. 3 is a timing diagram illustrating a method for reading data from the conventional DDR synchronous DRAM. Referring to FIGS. 1 and 2, in the system using the conventional DDR synchronous DRAM, a memory controller 11 generates an address ADD and a command signal COM (i.e., a write command signal WT, and a data strobe signal DQS. The memory controller 11 may also generate data DQ to be written into a DDR synchronous DRAM 15 within a module 13.
The DDR synchronous DRAM 15 receives the address ADD and the command signal COM in synchronization with a system clock CK. Next, the DDR synchronous DRAM 15 receives the data strobe signal DQS and the write data DQ, (i.e., D0 and D1). The data DQ is then stored in the DRAM 15 in response to a transition of the data strobe signal DQS from a logic 0 level (inactive) to a logic 1 level (active).
Referring now to FIGS. 1 and 3, the memory controller 11 generates the address ADD and the command signal COM (i.e., a read command signal RD), when data is to be read from the DDR synchronous DRAM 15. The DDR synchronous DRAM 15 receives the address ADD and the command signal COM in synchronization with the system clock CK and provides the data strobe signal DQS and the read data DQ (shown as D0 and D1).
The memory controller 11 receives the data strobe signal DQS and the data DQ from the DDR synchronous DRAM 15, during a read operation. The data DQ is received and latched by the controller 11 in response to a transition of the data strobe signal DQS from a logic 0 level to a logic 1 level.
However, in the conventional DDR synchronous DRAM, in order to write data at a desired rate into a memory cell during a write operation, JEDEC standards between the system clock CK and the data strobe signal DQS must be met. As shown in the input timing diagram of FIG. 2, the maximum skew between the system clock CK and the data strobe signal DQS is xc2xc of tCK, where tCK denotes the period of the system clock CK. Accordingly, an interval DQSWIN between a minimum time tDQSS (min) when the data strobe signal DQS is toggled during a write operation and a maximum time tDQSS (max) when the data strobe signal DQS is toggled is xc2xd of tCK.
Here, tDQSS (min) denotes the earliest time when the data strobe signal DQS reaches the DDR synchronous DRAM 15, measured from an edge of the system clock CK that occurs during an active period of the write command signal WT. tDQSS (max) denotes the latest time when the data strobe signal DQS reaches the DDR synchronous DRAM 15, measured from the edge of the system clock CK. As will be understood by those skilled in the art, tIS and tIH denote a setup time and a hold time of the write command signal WT and tDS and tDH denote a setup time and a hold time of the data DQ.
However, when the frequency of the system clock CK is increased (e.g., when the frequency of the system clock CK is increased to higher than 400 MHz (tCK=2.5 ns)), it may be difficult to manage the timing of the data strobe signal DQS so that the skew between the system clock CK and the data strobe signal DQS is xc2xc of tCK (e.g., less than 0.625 ns). Thus, as the data transmission speed is increased in response to higher clock frequencies, it may become more difficult to input valid data during the desired cycle of the system clock CK. Thus, notwithstanding higher data rates that can be achieved using DDR synchronous DRAMs, there continues to be a need for DRAMs that can handle skews greater than xc2xd tCK.
Integrated circuit memory devices according to a first embodiment of the present invention include a data latch having a data input, a control input and a clock input, and a strobe signal input buffer. The strobe signal input buffer is preferably responsive.to a data strobe signal and an indication signal. The strobe signal input buffer operates as a filter by selectively passing an inactive-to-active transition of the data strobe signal to the control input of the data latch when the indication signal is active, while blocking passage of the inactive-to-active transition of the data strobe signal to the control input when the indication signal is inactive. These filtering operations are preferably performed to inhibit the occurrence of data errors when excessive timing skew is present between a system clock and a data strobe signal at a given rate of speed. Accordingly, the operating speeds of memory devices according to embodiments of the present invention may be reliably increased. The data strobe signal and an unbuffered version of the indication signal are preferably generated by a memory controller, which may be operatively coupled to many memory banks within an integrated multi-bank memory system.
A multi-bank memory device according to a second embodiment of the present invention includes a synchronous dynamic random access memory (SDRAM) device. The SDRAM device preferably comprises a data latch circuit having a data input, a control input and a clock input. A strobe signal input buffer is also provided. This strobe signal input buffer is responsive to a data strobe signal and an indication signal. The strobe signal input buffer selectively passes an inactive-to-active transition of the data strobe signal to the control input of the data latch when the indication signal is active. Alternatively, the strobe signal input buffer blocks passage of the inactive-to-active transition of the data strobe signal to the control input when the indication signal is inactive. This blocking function is performed independent of the degree of timing skew between the system clock and the data strobe signal. The SDRAM device may also comprise a data input buffer having an output electrically coupled to an input of the data latch circuit.
A memory controller may also be provided to generate the data strobe signal and a data output of the memory controller may be communicatively coupled to an input of the data input buffer within the SDRAM device. The memory controller may also generate a pre-buffered indication signal and the SDRAM device may comprise an indication signal input buffer having an input that is responsive to the pre-buffered indication signal and an output at which the indication signal is generated as a time delayed version of the pre-buffered indication signal.
According to still another embodiment of the present invention, a multi-bank memory system is provided that comprises a memory controller and a memory device. The memory controller generates a data strobe signal and an indication signal. The memory device comprises a data latch circuit having a data input and a control input and an indication signal input buffer that generates a buffered indication signal in response to the indication signal. A preferred strobe signal input buffer is also provided. The strobe signal input buffer, which is responsive to the data strobe signal and the buffered indication signal, provides the control input of the data latch with a buffered version of the data strobe signal when the buffered indication signal is active. However, when the buffered indication signal is inactive, the strobe signal input buffer blocks generation of the buffered version of the data strobe signal.
Preferred methods of operating an integrated circuit memory devices also comprise the steps of generating data and an inactive-to-active transition of a data strobe signal in-sync with a clock signal. An indication signal is also generated. This indication signal has an inactive-to-active transition that precedes the inactive-to-active transition of the data strobe signal and an active-to-inactive transition that follows the inactive-to-active transition of the data strobe signal. According to a preferred aspect of these methods, a buffered data strobe signal is preferably generated as an inverted or non-inverted version of the data strobe signal when the transition signal is active and as an inactive signal, which is not a function of a state of the data strobe signal, when the transition signal is inactive.